/*
*	This is the regisiter between Memory and WriteBack
*	
*/

//TODO untested

module Reg_MW(
	//Input Signal
	RegWriteIn,
	MemtoRegIn,
	ReadDataIn,
	ALUOutIn,
	WriteRegIn,
	
	//Output Signal
	RegWriteOut,
	MemtoRegOut,
	ReadDataOut,
	ALUOutOut,
	WriteRegOut,
	
	//Clock Signal
	CLK,
	EN
);
	input RegWriteIn,MemtoRegIn,CLK,EN;
	input[31:0] ReadDataIn,ALUOutIn;
	input[4:0] WriteRegIn;
	
	output RegWriteOut,MemtoRegOut;
	output[31:0] ReadDataOut,ALUOutOut;
	output[4:0] WriteRegOut;
	
	reg RegWriteOut,MemtoRegOut;
	reg[31:0] ReadDataOut,ALUOutOut;
	reg[4:0] WriteRegOut;
	integer ClockCount;
	
	//initial
	initial begin
		RegWriteOut	=	0;
		MemtoRegOut	=	0;
		ReadDataOut	=	0;
		ALUOutOut	=	0;
		WriteRegOut	=	0;
		ClockCount	=	0;
	end
	
	//when CLR come through a posedge begin work
	always @(posedge CLK) begin
		if(EN == 1 && ClockCount == 0) begin
			RegWriteOut	<=	RegWriteIn;
			MemtoRegOut	<=	MemtoRegIn;
			ReadDataOut	<=	ReadDataIn;
			ALUOutOut	<=	ALUOutIn;
			WriteRegOut	<=	WriteRegIn; 
		end		
		ClockCount = (ClockCount+1)%2;
	end
endmodule
